The present invention relates generally to the manufacture of semiconductor devices and more particularly to a method of encasing areas of metallization to produce an intermediate structure that allows aggressive processing steps, prevents metal ion migration or electromigration, and increases packing density by using the encased areas of metallization as a self-aligned mask for etching cavities such as trenches or vias from an upper level of metallization through an intermediate dielectric to lower level circuits or metallization. The encapsulation and planarization after encapsulation provides a smoother surface for subsequent processing and enables the use of more effective and/or aggressive processing techniques such as chlorine-based RIE (Reactive Ion Etching) and consequently enables the creation of new device architectures.
As will be appreciated by those skilled in the art, most presently-used integrated circuit processing includes polishing of Damascene deposited copper or tungsten metal lines and vias. The resultant exposed copper or tungsten lines and vias are particularly susceptible to corrosion resulting from subsequent processing steps. Consequently, many of the more effective processing steps are simply too harsh to be used with such exposed copper or tungsten lines. Such limits on the available etching techniques and other processing requires costly modifications to a less expensive process flow that might otherwise be used. Therefore, it would be advantageous if the more effective, yet harsher, processing steps could be used on substrates containing copper or tungsten Damascene type integrated structures.
The present invention not only allows the use of very harsh processing steps, including chlorine-based etching steps, to be used with a copper or tungsten Damascene structures, but also controls out-diffusion or migration of harmful metal ions and atoms to adjacent sensitive circuits and may be used to provide a self-aligning mask for increasing the packing density of devices on a semiconductor chip.
For example, as will be appreciated by those skilled in the art, most semiconductor devices have several layers of circuits interconnected by vias etched through insulating and/or dielectric materials separating the two levels of circuits and filled with a conductive material such as, for example only, copper or tungsten. To avoid electrical shorts, it is very important that these vias filled with conductive metals do not unintentionally come into contact with other conductive lines and/or devices. Since electrical circuits and devices in an integrated chip are very small, a via that does successfully connect two levels of circuits together, but is misaligned by only a few tenths of microns may cause shorts and render a full wafer of devices useless. As will be appreciated by those skilled in the art, most misaligned vias are the result of a misaligned etching mask. Therefore, it is important that precautions be taken to be sure minor misalignment will not cause shorts. At present, one of the common ways to avoid such destructive electrical shorts is to increase the area that is allocated for the via etch. That is, increase the separation between circuits, or electrical conductive lines, and the location where the via is etched from an upper level to a lower level. This is, of course, a simple and effective solution. Unfortunately, since each of such multi-layer devices will typically include several vias, and since each wafer includes hundreds of devices, increasing the area for each via is also wasteful and decreases yield.
These and other problems are generally solved or corrected, and technical advantages are generally achieved, by embodiments of the present invention which provides methods and apparatus in a semiconductor structure to enhance further processing of the semiconductor. The methods and apparatus comprise a substrate with a dielectric having a top surface that defines at least one area of metallization having an exposed top surface such as is provided by a typical copper or tungsten Damascene process. For many applications, the area of metallization formed by the Damascene process will also include a protective liner or barrier covering the sides and bottom of the cavity, trench, or via before the copper or other metal is deposited. Suitable materials for the protective liner include, but are not necessarily limited to, Tantalum (Ta), Tantalum Nitride (TaN), Titanium (Ti), Titanium Nitride (TiN), Silicon Nitride (SiN), and Silicon Carbide (SiC). The top surface of the exposed copper or metallization is then recessed by any suitable processing step such as wet etching, RIE (Reactive Ion Etching) with, e.g., COxe2x80x94NH3 plasma for etching copper, IBE (Ion Beam Etching),or modified CMP (chemical-mechanical polishing). A layer of protective liner material, such as Ta, TaN, Ti, TiN, SiN, or SiC, is then deposited over the recessed top surface of the area of metallization to encase or encapsulate the area of metallization and may be planarized by a CMP (Chemical Mechanical Polish) to provide a very smooth top surface. The planarized encapsulated or protected areas of metallization provide a smoother surface for successive processing steps and also allow more aggressive or harsh processing steps. As a first example, a stack of magnetic films can be deposited over the dielectric layer and the protected areas of metallization. The magnetic stack of films can then be pattern etched with a chlorine-based RIE (Reactive Ion Etch), which is simply too corrosive to be used with exposed copper or tungsten lines. According to a second example, two neighboring encased areas of metallization can be used as the mask for etching a via from a top surface through the intermediate layer if the liner and encapsulation encasing the areas of metallization is a dielectric. A conductive metal, such as copper with metal liner, or tungsten, can then be deposited in the via in direct contact with material encasing the lines without short-circuiting the encased areas of metallization. According to a third use, the material encasing the areas of metallization will act as a barrier to migration or electromigration of metal ions or atoms, such as copper for example, into the vicinity of sensitive circuit components. Lastly, the encapsulation of the areas of metallization provides an effective adhesion promoter and protection against oxidation or corrosion so that a wider range of dielectrics can be utilized as films to be deposited on the areas of metallization. For example, one could use silicon oxide directly on the area of metallization without an intermediate silicon nitride layer, and thus reduce significantly the effective dielectric constant and capacitance of the structure.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.